1. Field of the Invention
The present invention relates to a nonvolatile memory device and a nonvolatile memory device manufacturing method, particularly to a nonvolatile memory device, in which a holding characteristic of a memory cell is improved, and a nonvolatile memory device manufacturing method.
2. Description of the Related Art
A nonvolatile memory device is known which has a nonvolatile characteristic that once stored data is not erased even if a power supply is turned off as long as the data is not erased or rewritten. As a cell structure of the nonvolatile memory device, a one-transistor-type memory cell structure is known. In case of this cell structure, an electric-charge storage film and a control gate are formed on a gate insulating film formed on a semiconductor substrate to have a structure laminated in this order. Electric charge stored in the electric-charge storage film corresponds to stored data. The one-transistor-type memory cell structure is classified based on the structure of the electric-charge storage film. That is, when the electric-charge storage film has a structure in which an interlayer insulating film is formed on a semiconductor region in which impurities are introduced, this structure is referred to as a floating-gate-type cell. When a structure in which a interlayer insulating film and an insulating film having many electric-charge trapping centers are laminated in order, this structure is referred to as MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor)-type cell. Also, when an electric-charge storage film has a structure in which an interlayer insulating film and an insulating film containing fine particles of the semiconductor are laminated in order, this structure is referred to as a nano-crystal-type cell. The insulating film containing fine particles of the semiconductor may further contain fine particles of metal. Also, when an electric-charge storage film is formed of ferroelectric substance or from a laminate film of a ferroelectric substance film and a metal electrode, this structure is referred to as an MF(M)IS (Metal-Ferroelectric-(Metal)-Insulator-Semiconductor)-type cell. In case of the nonvolatile memory device using the MFMIS-type cell, the direction of the spontaneous polarization of the ferroelectric substance included in an electric-charge storage layer corresponds to the data to be stored.
In these nonvolatile memory devices having the one-transistor-type memory cell structure, data write or read is commonly carried out by using a source, a drain and a control gate having the laminated structure formed on a semiconductor substrate around the cell structure and by controlling current flowing through a channel region between the source and the drain. Therefore, to improve the performance and reliability of the nonvolatile memory device having the structure, it is essential to sufficiently control physical properties of the channel region and the gate insulating film in the manufacturing process of the nonvolatile memory device.
Also, miniaturization of a memory cell is pursued in accordance with requests for increase of a memory device in capacity and decrease of the memory in size. According to the requests, a stress due to device separation influences a channel region. In case of the device separation by a shallow trench, an insulating film embedded in the trench applies compressive stress to the channel region in the direction parallel to the substrate surface. When the strong compressive stress is applied to the channel region, mobility of electrons decrease. In this case, because the on/off ratio of the current of the memory cell decreases, it is necessary to increase the electric charge quantity taken out from or injected into the electric-charge storage film through the gate oxide film. If the electric charge quantity to be taken out from or injected into the electric-charge storage layer increases, deterioration of the gate oxide film becomes extreme, on current is decreased and a holding characteristic of the memory cell is deteriorated. The compressive stress due to device separation in the shallow trench is similarly applied to the gate insulating film in addition to the channel region. When the strong compressive stress is applied to the gate oxide film, the activation energy of electron traps present in the gate oxide film is decreased. This means that electrons trapped in the electron traps are easily discharged, and therefore, the threshold voltage of a transistor is easily changed. This is a factor of holding characteristic deterioration.
Though the influence of the compressive stress on the channel region and gate insulating film is described above, the tensile stress also influences the memory cell. When the strong compressive stress is applied to the channel region and the gate insulating film, the coupling between dangling bonds and hydrogen atoms present in the interface between the gate insulating film and the semiconductor substrate is easily disconnected. Therefore, under the strong compressive stress, the number of interface levels in the interface between the gate insulating film and the semiconductor substrate increases, compared with a case of no stress. This means that the change of the threshold voltage of the transistor becomes large through the recovery of interface levels under the strong compressive stress. Therefore, the strong compressive stress is one of factors of deterioration of the holding characteristic.
In this way, in order to restrain the holding characteristic deterioration and to realize a high-reliability nonvolatile memory device, a technique is demanded which decreases the absolute value of the semiconductor substrate stress in the channel region. Such a technique makes it possible to increase the on/off ratio of the current of the memory cell, to restrain deterioration of the gate insulating film and to keep the characteristic of the memory cell. As a result, it becomes possible to improve the number of times of the rewriting operation and to realize the cell characteristic suitable for a multi-valued memory.
In conjunction with the above description, a manufacturing method of a nonvolatile semiconductor memory is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 8-31962). In this conventional example, it is aimed to form an interlayer insulating film not so as to deteriorate a gate insulating film. The nonvolatile semiconductor memory of the conventional example has a floating gate electrode is formed on a semiconductor substrate of a first conductivity type through a gate insulating film. A control gate electrode is formed on the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode is laminated on the floating gate electrode. Second conductivity type source and drain regions are formed separately from each other in the semiconductor substrate. As the interlayer insulating film, a single-layer oxide silicon film is formed by a chemical vapor deposition method. In this conventional example, it is described that deterioration of the gate oxide film is decreased because the stress of the interlayer insulating film is relaxed.